Driving a Vacuum Fluorescent Character Display
The following application uses a 5 x 7 40-digit VFD by Noritake. Each character is written in a single cycle since all 35 anodes (Al through A35) of the 5 x 7 matrix are pinned out. The characters (1 through 40) are scanned by selective control of their respective grid, each of which is pinned out (G1 through G40). Respective anodes of all characters (A1 of Char 1 through Char 40) are connected. This format is common to most dot character or segment character displays (Figure 8-64). Multirow displays require additional control. This is usually provided through parallel access to the anodes of each additional row (Table 8-5).
A typical driver scheme for a single line 40:5 x 7 dot character VFD is shown in Figure 8-65.
Whether or not the anode drivers require latched outputs depends on the circuit timing. Figure 8-66 shows a typical timing diagram for the display as shown in Figure 8-65. The drivers remain inactive for 183 µs (IDBT) prior to each character registration. This is more than sufficient time to load the 35 bits of data required for each character. With a 1 MHz data rate, the SN75513A requires only 35µS to load this information. Modification of the timing to take advantage of the latch capability
of the SN75512A for this particular application (1 line – 40:5 x 7 character VFD) will produce only minor improvement in display aesthetics. This is not the case for larger displays. Take for example, a six-line display of similar format (Table 8-5). A six-line display (DC40066A) requires control of 210 anodes (6 x 5 x 7). Thus, unless received in parallel format, this requires 210µs loading time. With a latched driver however, this presents no problem as new data can be entered independent of the IDBT. Figure 8-67 illustrates a typical timing diagram incorporating this design.
The latch function virtually extends the time allotted for data registration in the anode drivers to the full character cycle time. For a 100 Hz panel refresh rate (Tr = 10 ms) and 1:150 minimum character duty cycle, the minimum character cycle time is 67µS (Tp = TrXDC = 10 ms/150). The larger the panel the more complex the anode/grid configuration, the more beneficial the latch feature (as that available with the SN75512A) becomes.
Driving a Dot Matrix Display
As discussed in a preceding section of Panel Performance, several variation of grid/anode configurations exist. The following will present the panel requirements and suggested drive techniques for the displays shown in Figures 8-55(b), (c), and (d).
Figure 8-68 illustrates the VFD grid/anode arrangement for a DM256X64A. This is a 256 x 64 dot matrix VFD by Noritake whose grid/anode configuration is as illustrated in Figure 8-55.
Figure 8-69 shows the required timing of the anode and grid signals to properly operate the DM256X64A. As can be seen in Figures 8-68 and 8-69, the active columns are composed of anodes which are between the activated grids. When grids 1 and 2 are activated, columns 2 and 3 are between them, and columns 1 and 4 are outside them. The purpose of this arrangement is to eliminate fringing effects of neighboring grids and thus achieve uniform intensity. Analysis of this configuration also shows requirements on panel drive electronics which are common to the previous examples. If the total panel refresh rate is held to 100 Hz, the total panel period (Tr) is 10 ms. With 128 write cycles required, each write cycle is 78µS (Tc). Maintaining the 1:150 duty cycle, each strobe signal is 66 tJ-S (T p). This allows only 12µS dead time or IDBT which dictates the use of an active pull-down driver. The time between the strobe signals of a particular anode group is 90µS. This opens options in the VFD driver architecture. Each group of anode drivers requires 64 bits of data and two groups (A & D or B & C) must be loaded during each column write cycle (128 bits). If the SN75512A is used, its latch feature allows use of total strobe cycle period (156 µs), and a 1 MHz data rate allows the data to be received in a serial format. If the SN75513A is used, the A(B) group and D(C) group data must be loaded in parallel (64 us), since it must be loaded during the dead time between strobe signals. Also available is the SN75501C. Since the strobe signal duty cycle is less than 50%, the SN75501C can also be used.
With a 4 MHz data rate, all 128 bits of data can be registered serially in a 32 µS dead time between strobes. Figures 8-70 through 8-73 illustrate the dot matrix pinout and timing diagrams for the anode/grid configurations shown in Figures 8-55(c) and 8-55(d). Table 8-6 identifies applicable anode and grid drivers and the number required for each of the configurations presented.