uA2240 Programmable Timer/counter

The uA2240 programmable timer/counter is a special class of timer IC. This device includes a timing section made up of a timer similar to a 555 type, an eight bit counter, a control flip-flop, and a voltage regulator. Timing periods from microseconds to days may be programmed with an accuracy of 0.5%. Two timing circuits cascaded could generate time delays of up to three years. The 2240 may be operated in either the monostable or astable mode with programmable timing in either mode. A functional diagram and pin-out are shown in Figure 7-9.

Voltage Regulator (VREG)

The on-chip regulator provides voltage to the binary counter and control logic and through pin 15 to external circuits. If VCC (pin 16) is 15 V. VREG is typically 6.3 V. For a VCC of 5 V. VREG is typically 4.4 V. For a VCC

Figure 7-9. uA2240 Functional Block Diagram and Pinout

supply of less than or equal to 4.5 V. pin 16 (VCC) should be shorted to pin 15 (VREG). The minimum supply voltage for this condition is 4 V. When supplying external circuitry via pin 15 (regulator output), the output current should be 10 mA or less.

Control Logic

The control logic block provides trigger and reset signals to the binary counter and time-base generator flipflops. Trigger and reset inputs are high impedance and TTL compatible, requiring only about 10µA of input current. Therefore, they may be controlled by TTL, low level MOS or CMOS logic, and respond to positive input transitions. The reset input (pin 10) terminates the timing cycle by returning the counter flip-flops to zero and disabling the time-base oscillator. A logic-high reset stops the timer and sets all outputs high. When powered on, the uA2240 comes up in the reset state. A trigger input (pin 11) initiates the timing cycle by enabling the time base oscillator and setting all outputs low. Once triggered, the circuit is immune to further trigger inputs until the timing cycle is completed or a reset signal is applied. However, the trigger takes precedence if both trigger and reset are applied simultaneously.

Time-Base Oscillator

The heart of a uA2240 is its time-base oscillator that is made up of threshold comparators, a flip-flop, discharge and time-base output transistors, RC input, and a modulation and sync input.

RC Input

A resistor and capacitor connected in series between VCC and ground provide an exponential ramp at the RC input (pin 13). The comparator thresholds are designed to detect at levels allowing a 63% charge time (1 RC time interval). Thus, the time-base output (TBO) pulse will have a period T = 1 RC. Figure 7-10 shows the recommended range of timing component values. The timing capacitor leakage currents must he low to allow it to charge to the comparator threshold levels with a large value (1 MΩ or greater) timing resistor.

Figure 7-10. Recommended Range of Timing Component Values

Modulation and Sync Input

The MOD input (pin 12) is nominally at 73% of the VCC level due to internal biasing. This level may he varied by connecting a resistor from pin 12 to ground or VCC, or by applying an external voltage. This change, or modulation, of voltage on pin 12 changes the upper threshold for the time-base comparator resulting in a change, or modulation, of the time-base period T. Figure 7-11 illustrates the effects of an externally applied modulation voltage on the time-base period.

Figure 7-11. Normalized Change in Time Base Period as a Function of Modulation Voltage at Pin 12

The MOD input may also be used to synchronize the time-base oscillator with an external clock. Synchronization is achieved by setting the time-base period (T) to be an integer multiple of the sync pulse period (TS). This is accomplished by choosing R and C timing components so that:

Figure 7-12 gives the typical pull-in range for harmonic synchronization versus the ratio of time-base period to sync pulse period (T/TS).

Threshold Comparators

The two levels of threshold are set at 27% and 73% of VCC. Charging and discharging of the timing capacitor

Figure 7-12. Typical Pull-In Range for Harmonic Synchronization

occurs between these two levels. When charging from the 27% level toward VCC to the second threshold at 73%, the percentage interval to be changed is 73 – 27 or 46%. The actual percentage of the range from 27% to the VCC rail is 73% so the charge range to be covered is 0.46/0.73 or 63%, exactly one RC time constant. The’ resulting time base T = RC.

Oscillator Flip-Flop

Comparator outputs feed the oscillator flip-flop which controls the discharge and time-base output (TBO) transistors. Once triggered (see Figure 7-13) the oscillator continues to run until reset. Output pulses from the TBO are internally connected to the counter input for automatic triggering. The TBO output is an open-collector transistor and requires a pull-up resistor (typically 20 kΩ) to be connected to the VREG output (pin 15). Grounding the TBO output (pin 14) will disable the counter section. NOTE: When using a high supply voltage

(VCC> 7 V) and a small timing capacitor (C <0.1 µF) the pulse width of the TBO output may be too narrow to trigger the counter section. Connecting a 300 pF capacitor from pin 14 to ground will widen the TBO output pulse width and allow a proper trigger time. This capacitor is also recommended to improve noise immunity.

Binary Counter

The uA2240 has an on-chip 8-bit binary counter with outputs that are buffered open-collector type stages. Each output is capable of sinking 2 mA at 0.4 V VOL. At turn on, or in the reset condition, all counter outputs are high, or in the off state. Following a trigger input (Figure 7-14) the outputs will change states according to the sequence shown. The outputs may be used individually, or can be

Figure 7-13. Timing Diagram

connected together in a wired-OR configuration for special programming. Combining counter outputs in a wired-OR configuration results in the addition of the time delays associated with each output connected together. As an example pin 5 alone results in a timing cycle (TO) that is equal to 16T. Similarly connecting Q0 (pin 1), Q4 (pin 5), and Q7 (pin 8) together will yield TO = (1 + 16 + 128) T = 145 T. A proper selection of counter output terminals will allow programming of TO from 1 T to 255 T.

Monostable Operating Mode

Figure 7-15 illustrates the 2240 used in the monostable mode. In the circuit, Figure 7-15(a), Rt and Ct set the time base T, for the desired time period, TO, Programming of various output times may be accomplished by connecting the desired counter output pins together. The timer output appears across RL. The output pulse width. TO, is equal to the number of timing pulses, n, multiplied by RtCt or TO = nRtCt.

As shown in the timing diagram. Figure 7-15(b), the output is high (at VCC) prior to triggering. When a trigger pulse is received, the output falls low and the timing cycle is initiated. The time-base oscillator will now run until the counter reaches the count programmed by the selector switches or jumpers. When this count is reached, the output rises from the low level to VCC. This rise in level is fed to the reset input, which stops the oscillator and resets the counter. The timer is now in its standby state, awaiting the next trigger pulse. R1 is a load resistor for the time-base output. The 270 pF capacitor on the time-base pin is a noise bypass to

Figure 7-14. Timing Diagrams of Output Waveforms

ensure noise immunity within the time-base oscillator. The Rt and Ct value ranges appear in Figure 7-15. The maximum oscillator frequency should be limited to about 100 kHz.

Astable Operating Mode

The astable mode circuit is shown in Figure 7-16(a). This circuit is similar to the monostable circuit with the exception that the reset is not connected to the output. This allows the oscillator to continue oscillating once started by a trigger pulse. With a single counter output connected to RL and the output bus, the frequency of oscillation will be:

The factor 2 is required because the basic timing taps are multiples of 1/2 cycle. This circuit will not self-start on power-up. A pulse applied to the trigger input will start the synchronous oscillations. The oscillator may be stopped by applying a reset pulse, which causes the output to go high. It will remain in this state until triggered again. If automatic power-up oscillation is desired, connect the trigger input to pin 15 (regulator output). The timing component ranges shown in the monostable circuit. Figure 7-15, are applicable to the astable mode circuit.


The 2240 timer is somewhat more complex than the 555 family. Timing accuracy is good, typically 0.5% at a VCC of 5 V. The maximum operating frequency is about 130 kHz. The trigger and reset inputs have a threshold sensitivity of 1.4 V.


Several precautions should be taken with respect to the VCC supply. The most important is good power supply

Figure 7-15. uA2240 Monostable Mode Circuit

filtering and bypassing. Ripple on the supply line can cause loss of timing accuracy. A capacitor from VCC to ground, ideally directly across the device, is necessary. The capacitance value will depend on the specific application. Values of from 0.01µF to 10µF are not uncommon. The capacitor should be as close to the device as physically possible.

If timing accuracy is to be maintained, stable external components are necessary. Most of the initial timing error is due to the inaccuracies of the external components. The timing resistors should be the metal film type if accuracy and repeatability are important design criteria. If the timing is critical, an adjustable timing resistor is necessary. A good quality multi-turn pot might be used in series with a metal film resistor to make up the R portion of the RC network.

The timing capacitor should also be high quality, with very low leakage. Do not use ceramic disc capacitors in the timing network under any circumstance. Several acceptable capacitor types are silver mica, mylar, polystyrene, and tantulum. If timing accuracy is critical over temperature, timing components with a small positive temperature coefficient should be chosen. The most important characteristic of the capacitor is low leakage. Obviously any leakage will subtract from the charge count causing the actual time to be longer than the calculated value.

One final precaution should be observed. Make certain that the power dissipation of the package is not exceeded. With extremely large timing capacitor values, a maximum duty cycle which allows some cooling time for the discharge transistor may be necessary.


Figure 7-17 illustrates an NE555 timer utilized as a missing pulse detector. This circuit will detect a missing pulse or abnormally long spacing between consecutive pulses in a train of pulses. The timer is connected in the monostable mode. In addition, a 2N2907 is connected with the collector grounded and the emitter tied to pins 6 and 7. This outboard switch is in parallel with the internal discharge transistor. The transistor base is connected to the trigger input of the NE555.

For this application, the time delay should be set slightly longer than the timing of the input pulses. The timing interval of the monostable circuit is continuously

Figure 7-16. uA2240 Astable Mode Circuit
Figure 7-17. Missing Pulse Detector Circuit

etriggered by the input pulse train (V1). The pulse spacing is less than the timing interval, which prevents VC from rising high enough to end the timing cycle. A longer pulse spacing, a missing pulse, or a terminated pulse train will permit the timing interval to be completed. This will generate an output pulse (VO) as illustrated in Figure 7-18. The output remains high on pin 3 until a missing pulse is detected at which time the output goes low.

Figure 7-18. Missing Pulse Detector Waveform

The NE555 monos table circuit should be running slightly slower (lower in frequency) than the frequency to be analyzed. Also, the input cannot be more than twice this free-running frequency or it would retrigger before the timeout and the output would remain in the low state continuously. The example in Figure 7-17 operates in the monostable mode at about 8 kHz so pulse trains of 8 to 16 kHz may be observed.