The SN75514 (Figure 8-61) is similar to the SN75512A except it is capable of operating at up to 125 instead of 60 V. Although not limited to high density, applications, the SN75514 was designed to accommodate the specific requirements of large, high resolution (dot matrix) VF displays: high anode driver voltages, high-speed data reception and short inter-digit-blanking times (higher duty cycle).
As with the SN75512A, the 12-bit serial-in, parallel-out shift register is loaded on the positive edge of clock transition. However, the SN75514 combines the latch enable and output strobe functions of the 60 V device in one control line (strobe). Valid data is transferred from the shift register to the parallel latch outputs when the active-high strobe line is taken low. This is truly an edge-triggered data transfer as changes in the shift register contents while the strobe is held low will have no effect on the latch contents. With the strobe held low, high-voltage output lines go low (disabled state) and remain low until the strobe goes high. Upon raising the strobe line to a logic one, the latch contents are presented to the display through the high-voltage outputs (enabled state).
Another difference between SN75514 and the SN75512A lies in the high voltage supply requirements. Whereas a single supply of up to 70 V (VCC2) was sufficient with the lower voltage device, the SN75514 requires two high-voltage supplies to deliver the maximum 25 mA per channel current drive capability. VCC2 (130 V, absolute maximum) provides the actual current to the display load through a high-voltage transistor in the output totem-pole structure. However the bias of that DMOS switch requires a slightly higher voltage (VCC2 + 10 V) to be applied to the VCC3 input. Often, these two voltages can be obtained from one supply and a few passive components. In addition, it is possible to operate the device with VCC2 and VCC3 in common, with the only penalty being reduced current source capabilities on the high voltage outputs.
The inputs are directly compatible with CMOS logic and can be interfaced with TTL with the addition of pullup resistors.