Monday , September 23 2019

Positive Peak Detector Circuit Design By TLC251 Lincmos Op Amp

Peak detectors measure and hold the maximum value of a fluctuating voltage. The purpose of the circuit in Figure 3-39 is to hold the peak of the input voltage on capacitor C1, and read the value, VO, at the output of U2. Op amps U1 and U2 are connected as voltage followers. When a signal is applied to V1, C1 will charge to this same voltage through diode D1. This positive peak voltage on C1 will maintain VO at this level until the capacitor is reset (shorted). Of course, higher positive peaks will raise this level while lower peaks will be ignored. C1 can be reset manually with a switch, or electronically with an FET that is normally off.

The capacitor specified for C1 should have low leakage and low dielectric absorption. Diode D1 should also have low leakage. The op amps selected for use in a peak detector should be immune to instability due to capacitive loading, and have high output drive and slew rate. They should also have very low input bias currents and extremely high input impedance. The TLC251 meets these requirements well. The TLC251 allows the reading of low-level signals near ground because its input-common-mode range includes the negative connection to the power supply. Peak values of negative polarity signals may be detected by reversing D1.

Figure 3-39. Positive Peak Detector and Waveform

 

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