NE/SE555 Timers Definition Block Diagram Functions Rs Flip-flop Operating Modes & Many More


The NE555 was the first monolithic IC timer with multi-functional capabilities (introduced in 1972) and has been accepted as the standard for basic timing and oscillator functions. The NE555 (Figure 7-3) is a general-purpose bipolar IC capable of monostable and astable pulse generating modes covering a wide range of pulse durations and/or frequencies.


Threshold Comparator

The threshold comparator compares its input with an internal reference level that is 2/3 VCC. An input level greater than the reference will reset the timer’s flip-flop resulting in a low output level and causing the discharge transistor to turn on. The internal reference is brought out on a pin allowing external control of the reference level to modify the timing period or reset the comparator. If this pin is not used it should be bypassed with a 0.01µF capacitor to improve the timer’s noise immunity.

Trigger Comparator

The trigger comparator compares its input with an internal reference level that is 1/3 VCC. An input level less than 1/3 VCC will set the flip-flop causing the output to go high and the discharge transistor to turn off. The trigger comparator functions on the leading (negative going) edge of the input pulse. Typically a minimum input pulse duration of 1.0µs is required for reliable triggering. If the trigger input level remains lower than 1/3 VCC for longer than one timing cycle, the timer will retrigger itself after the first output pulse. Propagation delay in the trigger comparator can delay turn off up to several microseconds after triggering. An output pulse duration of 10µs or greater will prevent double triggering due to these effects.

RS Flip-Flop

The RS flip-flop receives its reset input from the threshold comparator, its set input from the trigger comparator and an additional reset from an external source. The external reset input overrides all other inputs and can be used to initiate a new timing cycle. When this input is at a logic low level the timer output is low and the discharge transistor is on, resulting in a reset condition. The reset input is TTL compatible. When not used it is recommended that the reset pin be connected to the VCC rail to prevent false resetting.

Discharge Transistor

The discharge transistor will be on when the device output is low. Its open-collector output is used to discharge the external timing capacitor during the reset phase of operation.

Output Stage

The device output stage is driven by the flip-flop output. It is an active-pull-up, active-pull-down circuit with a 200 mA sink or source capability.


There are two basic operating modes for 555 timer circuits: the monostable (one-shot) mode for timing functions, and the astable (free-running) mode for oscillator functions. There are many variations of the two basic modes, allowing numerous applications.

Figure 7-3. NE555 Timer Block Diagram

Monostable Mode

Figure 7-4 illustrates the circuit and waveforms for the 555 connected in its most basic mode of operation – a triggered monostable. With the trigger input terminal held higher than 1/3 VCC, the timer is in its standby state and the output is low. When a trigger pulse appears with a level less than 1/3 VCC, the timer triggers and its timing cycle starts. The output switches to a high level near VCC and concurrently Ct begins to charge toward VCC. When the VC voltage crosses 2/3 VCC, the timing period ends with the output falling to zero. The circuit is now ready for another input trigger pulse. The output pulse duration (T) is defined as (1.1) x RtCt. In the monostable mode T is used to represent the on time which is the time base in this mode. With few restrictions, Rt and Ct can have a wide range of values. Assuming zero capacitor leakage current, there is no theoretical upper limit on T while the short pulse durations are limited by internal propagation delays to about 10µS.

Figure 7-4. 555 Triggered Monostable Circuit

A reasonable lower limit for Rt for 15 V operation, is about 1 kΩ for the NE555 and is limited only by power dissipation considerations. The upper Rt limit, for a VCC of 15V, is about HI MH. Allowing for only 0.25µA input leakage and 0.25µA capacitor charging current the total current through Rt at the threshold level would be 0.5µA. Rt max is equal to the voltage across Rt at threshold, (which for a 15V supply is 5V), divided by 0.5µA. This yields an Rt max of 10MΩ. However, lower values should be used if accurate timing is required.

A practical minimum value for Ct is about 100 pF. Below this value stray capacitance becomes a limiting factor for timing accuracy. The maximum value for Ct is limited by capacitor leakage. Low leakage capacitors are available in values up to about 10µF and are preferred for long timing periods. Capacitor values as high as 1000µF could possibly be used if the leakage current is low enough for the application. The real limitation on Ct is leakage current and not capacitance. The ultimate criterion for the selection of Rt and Ct is the degree of accuracy desired. Staying within the limitations illustrated in the 555 device data sheet charts is recommended for relatively accurate designs.

As given in Figure 7-4(b), the pulse duration T is slightly more than an RC time constant (T = 1.1 RC). This is a result of a threshold level that is 66.7% of VCC while one RC level is 63.2% of VCC.

In a typical application input leakage currents may also lead to some slight differences between actual values of “T” and alculated values. Operation at high speeds (very short pulse durations) will result in variations from the calculated values due to internal propagation delays.

Astable Mode

Figure 7-5(a) illustrates the 555 connected as an astable timer. Like the monostable circuit, the astable circuit requires only a few external components. Figure 7-5(b) shows the timing diagram. The timing calculations are as follows.

On startup, the voltage across Ct will be near zero which causes the timer to be triggered via pin 2. This forces the output high, turning off the discharge transistor and allows charging of Ct through RA and RB. Ct charges toward VCC until its voltage reaches a level of 2/3 VCC, at which point the upper threshold is reached, causing the output to go low and the discharge transistor to turn on.

Figure 7-5(a). 555 Astable Circuit
Figure 7-5(b). NE555 Astable Timing Diagram

Capacitor Ct then discharges toward ground through RB until its voltage reaches 1/3VCC, the lower trigger point. This retriggers the timer, beginning a new cycle. The timer threshold input therefore oscillates between the 2/3 VCC and 113 VCC comparator threshold levels.

The frequency of operation is simply the reciprocal of T as stated above. The duty cycle for either the high or low output state is simply that period (t1 or t2) divided by the total period. For reliable operation, the upper frequency limit of the bipolar NE555 is about 100 kHz. Device upper frequency limitations are due to internal propagation delays. Low frequencies are not limited by the 555 devices but are limited by the leakage characteristics of Ct.

Specific duty cycles may be required in some applications. Duty cycle can be controlled (within limits) by adjusting the resistance ratios of RA and RB in Figure 7-5(a). As RB becomes large with respect to RA, the duty cycle approaches 50% (square wave operation). Conversely, as RA becomes large with respect to RB, the duty cycle increases toward 100%. RA must not be allowed to reach zero. Practical duty cycles range from 49.8% to 99% or in terms of resistor ratios RA may be 1/100 of RB or RB may be 1/100 of RA.


Although the 555 is a simple device, it performs accurately. In the monostable mode there is a typical initial error of only 1% due to process imperfections (Rt and Ct errors must be considered separately). For astable operation the error is somewhat greater, typically about 2%. Drift with temperature is typically 55 ppm/oC (or 0.005%/oC) for the monostable mode, and is about 150 pprn/oC for the astable mode.