Bus Interface Devices

Interfacing between the instrument (or apparatus) interface functions and the system bus is accomplished with line driver and receiver circuits generally configured as transceivers. Since IEEE-488 systems consist of eight data lines and eight control lines, interfacing to the bus is often accomplished with octal transceivers. Details concerning the characteristics of these devices are covered in the following section on Electrical Specifications.

Electrical Specifications 

Electrical specifications for driver output and receiver input voltage levels are the same as TTL voltage levels. However, a negative logic convention is used and is defined as follows:

LOGIC STATE VOLTAGE LEVEL
ZERO >2.0 V (high state)
ONE <0.8 V (low state)

For this discussion, current flow into a node carries a positive sign and current flow out of a node carries a negative sign.

Driver Requirements 

Drivers with open-collector outputs shall be used to drive the SRQ, NRFD, and NDAC signal lines. Drivers with open-collector or three-state outputs may be used to drive data I/O (lines 1-8). DAV, IFC, ATN, REN, and EOI signal lines with the following exception: Data I/O (lines 1-8) shall be driven by open-collector output drivers for parallel polling applications. Three-state driver outputs are used for systems where maximum operating speeds are required. A three-state driver output is also recommended to drive the ATN signal line if the controller is intended to be used in a system where other devices are implemented with three-state drivers on the DIO, DAV, and EOI signal lines.

Driver Specifications 

Driver outputs shall meet the following specifications:

  • Low state output voltage (three-state or open-collector output) <0.5 V at 48 mA sink current.
  • The driver shall be capable of sinking 48 mA continuously.
  • High state output voltage (three-state) >2.4 V at -5.2 mA.
  • High state output voltage (open-collector) dependent on resistive load termination. 

Receiver Specifications 

Required input signal levels, necessary to provide nominal noise margins, shall be as follows:

  • Low state input voltage <0.8 V
  • High state input voltage >2.0 V

Preferred input signal characteristics, necessary to provide added noise margin and improved reliability, are as follows:

  • Receiver input hysteresis, Vt pos – Vt shall be >0.4 V
  • Low state negative going threshold voltage Vt neg >0.8 V
  • High state positive going threshold voltage Vt <2.0 V

Composite Load Requirements 

The total dc load characteristics primarily result from resistive line terminations and receiver input characteristics. Negative voltage clamp circuits and driver high-impedance output state characteristics result in some slight additional loading.

Figure 9-107 illustrates a typical circuit configuration whose specifications are as follows:

  • RLl (line to VCC) is 3 kΩ ±5%
  • RL2 (line to ground) is 6.2 kΩ ± 5%
  • Driver output leakage current:
    • open-collector driver is 0.25 mA maximum
    • three-state driver is ± 40 µA maximum at VO = 2.4 V
  • Receiver input current:
    • – 1.6 mA maximum at VO = 0.4 V
  • Receiver input leakage current:
    • 40 µA maximum at VO = 2.4 V
    • 0 mA maximum at VO = 5.25 V
  • VCC: 5.0 V ± 5%
Figure 9-107. Typical Signal Line I/O Circuit

Device DC Load Line Boundaries 

The load conditions of a device assume that the driver, receiver and termination network are internal to the device and that the driver is in its high-impedance state. The signal line interface to the device shall have a dc load characteristic that falls within the unshaded area illustrated in Figure 9-108. The load line boundary limits are defined as follows:

  1. If I <0 mA, V is <3.7 V.
  2. If I >0 mA, V is >2.5 V.
  3. If I > – 12.0 mA, V is > – 1.5 V.
  4. If V <0.4 V, I is < – 1.3 mA.
  5. If V >0.4 V. I is > -3.2 mA.
  6. If V <5.5 V, I is <2.5 mA.
  7. If V >5.0 V, I is >0.7 mA
Figure 9-108. DC Load Line Permissible Operating Area

Device AC Load Line Limit 

The small-signal load impedance shall be <2.0 kΩ at 1 MHz.

Device Capacitive Load Limit 

Each device shall present an internal capacitive load of <100 pF to each of its signal lines.

Timing Values 

Definite relationships between critical signal inputs and outputs are required for successful interconnection of devices. Consideration of propagation delays, transition times and system response times is necessary for reliable operation.

Table 9-13 lists several of the required limits on these timing values. The longer time values shown allow for the inherently long propagation delays of the transmission lines as well as device circuit delays. The IEEE-488 Standard has a detailed discussion of these timing requirements.

Data Rates 

Open-collector drivers will operate at a maximum of 250.000 bytes per second. Three-state drivers with equivalent standard loads will operate at a maximum of 500.000 bytes per second. With special precautions (three-state drivers, short signal lines and minimum capacitive loading) data rates up to 1 megabyte per second are possible.